Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors
Jong‐Ho Bae, Daewoong Kwon, Namho Jeon, Suraj Cheema, Ava J. Tan, Chenming Hu, Sayeef Salahuddin
Abstract
In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) as gate insulator. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\Omega }$ </tex-math></inline-formula> -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> endurance cycles. The impact of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {D}}$ </tex-math></inline-formula> on erase speed provides insights into the importance of holes on memory operation.