Harmonics Reduction of Adjustable Speed Drive Using Transistor Clamped H-Bridge Inverter Based DVR With Enhanced Capacitor Voltage Balancing
Anurag Khergade, R. J. Satputaley, Vijay B. Borghate, BVS Raghava
Abstract
Harmonics generated by nonlinear critical loads are major anxiety for the industries. A control technique for dynamic voltage restorer (DVR) is described to limit voltage harmonics introduced by adjustable speed drive (ASD) in the utility. Moreover, this control technique maintains constant dc-link voltage of ASD during any disturbances occurring at point of common coupling. Mathematical description to limit ASD voltage harmonics and to generate reference dc-link voltage of ASD is illustrated in the dq0 frame. Transistor clamped H-bridge (TCHB) multilevel inverter (MLI) is used as a voltage source inverter of DVR. An enhanced capacitor voltage balancing (ECVB) method for TCHB MLI for the fast dynamic performance of DVR is also discussed. The proposed control technique of DVR to limit ASD voltage harmonics is simulated using MATLAB software. Furthermore, a simulation for DVR protecting ASD during source harmonics, unbalance, sag, and swell is carried out and results of ASD performances are demonstrated. The working of the proposed controller of DVR with ECVB strategy based TCHB is reverified using experimental results. ASD voltage harmonics mitigation and fast dynamic response of ECVB based TCHB are the highlights of this article. The performance of the proposed strategy shows satisfactory results with a less complex control system.