Investigation of Gate-Length Scaling of Ferroelectric FET
Sourabh Jindal, S. K. Manhas, Satendra Kumar Gautam, Simone Balatti, Arvind Kumar, Mahendra Pakala
Abstract
In this article, the device scaling of FeFET down to 22 nm and its impacts on memory performance and reliability has been investigated in detail using experimentally calibrated data. Lateral nonuniformity along the channel in the polarization of the ferroelectric layer is observed, which is shown to be due to the scaling effects in FeFET. It has been observed that with gate-length scaling, the remnant polarization shows opposite trends, i.e., ${P}_{r}$ reduces for program and increases for erase. Also, with scaling, there is a significant rise in the electric field across the interfacial layer for erase state, which is an important concern for reliability. We find a relatively stable memory window with gate-length scaling due to the counter-balancing of $\pm {P}_{r}$ . Gate-length scaling has resulted in a larger decrease in ${V}_{\text {th}}$ and higher subthreshold slope (SS) for program state due to a reduction in gate control as compared to erase state. Our results provide important insights into the design optimization of nanoscale FeFET for high-density and low-power applications.