A 2.65-pJ/Bit 12.5-Gb/s 60-GHz OOK CMOS Transmitter and Receiver for Proximity Communications
Chul Woo Byeon, Ki Chan Eun, Chul Soon Park
Abstract
This article presents a high data rate, high-efficiency 60-GHz on-off keying (OOK) CMOS transmitter and receiver. The transmitter consists of a voltage-controlled oscillator (VCO) and a modulator. The receiver consists of a low-noise amplifier, detector, and limiting amplifier (LA) and has a compact design. An analysis of the on-off isolation of the modulator and bandwidth of the LA reveals that the proposed transformer (TF) between the modulator and the VCO can improve the on-off isolation, and the feedforward capacitor can enhance the bandwidth. Implemented in the 65-nm CMOS technology, the transmitter and the receiver consume dc powers of 12.1 and 21 mW, respectively, at 12.5 Gb/s. Moreover, they occupy core chip areas of 0.09 and 0.06 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively. The transceiver system is constructed with on-board Yagi-Uda antennas, and it achieves 12.5 Gb/s wireless OOK data transmission for a pseudorandom binary sequence of length 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 with a bit error rate of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> . The proposed transceiver system achieves an energy efficiency of 2.65 pJ/bit.