Transformer-less multilevel inverter (TMLI) with reduced device count and voltage stress
Kasinath Jena, Rishi Kesh, Dhananjay Kumar, Aditya Prasad Padhy, Md Irfan Ahmed, Chinmoy Kumar Panigrahi
Abstract
The paper introduces a new transformer-less step-up switched capacitor topology that utilizes twelve switches to create nine different voltage levels. The salient features of the proposed topology are the least switching components, zero leakage current, boosting capability and reduced voltage stresses. Furthermore, the capacitors possess inherent self-balancing properties, eliminating the requirement for an extra circuit to achieve capacitor self-balancing. The paper provides concise explanations of the operational principle, modulation scheme, and loss analysis. A brief comparative analysis of the existing topologies demonstrates the advantages and superiority of the proposed approach. Additionally, the theoretical concept and feasibility of the new topology are verified through simulations and experimental results. Without a filter, the THD at the output voltage and current of the proposed inverter has been measured at 16.48% and 0.88%, respectively.