Ultra Low power SRAM Cell for High Speed Applications using 90nm CMOS Technology
Hansraj, Alka Chaudhary, Ajay Rana
Abstract
SRAM is employed as a cache memory within the processor associate degree additionally has an application of the integrated system. With the continuing advancement of microcircuit technology, the density of SRAMs in embedded applications has adult well in recent years. The power dissipation of the projected new SRAM cell is sort of stable for top speed operations. Since the amount of transistors and therefore the space has exaggerated compared to the standard SRAM 6T cell, this disadvantage will simply be overcome by low power dissipation even at terribly high frequencies. During this paper, we have a tendency to propose a replacement lowpower SRAM model for high speed operations. This new style approaches the voltage mode methodology to scale back voltage swing around writing switch activity. Within the standard SRAM cell thanks to method variation, the hold on knowledge is also destroyed throughout the read operation. As a result, the outpouring current thanks to bigger power dissipation is reduced. Dynamic power is calculated for various frequencies and compared to the standard SRAM 6T cell. During this proposed methodology, the new SRAM cell may be accustomed offer low-power consumption of high-speed devices like laptops, smart phones, programmable logic devices, and so on. The results of the simulations show that the frequency of the projected SRAM model additionally will increase; the facility dissipation is almost constant. This ensures reduced energy dissipation for prime frequency SRAM CMOS cell layout. The projected style is simulated on the LT SPICE IV using 90nm CMOS technology.