An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine
Justin M. Correll, Jie Lu, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, N. Breil, Roger Quon, Deepak Kamalanathan, Siddarth Krishnan, M. Chudzik, Zhengya Zhang, Wei Lü, Michael P. Flynn
20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)47 citationsDOI
Abstract
Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
Topics & Concepts
Resistive random-access memoryTOPSComputer scienceBit (key)Computational scienceParallel computingComputer hardwareElectrical engineeringMathematicsEngineeringAzimuthComputer securityGeometryVoltageFerroelectric and Negative Capacitance DevicesAdvanced Memory and Neural ComputingAdvanced Data Storage Technologies