A New Scheme of the Low-Cost Multiple-Node-Upset-Tolerant Latch
Xiaole Cui, Qixue Zhang, Xiaoxin Cui
Abstract
The single event upset (SEU) in integrated circuit (IC) occurs due to the striking of heavy charged particles. It results in the multiple node upset (MNU) problem frequently, with the scaling down of semiconductor devices. To address this challenge, the radiation hardening by design (RHBD) methods of circuit are required, in addition to the layout and device level radiation hardening techniques. The latch is one of the basic components of logic circuit, and the RHBD method of latch circuit is still an open issue. The Muller C-element (MCE) and/or the dual interlocked storage cell (DICE) based RHBD methods for latch circuit introduce too much area overhead, because of the redundant circuit structures. This work proposes a new design method of the low-cost multiple-node-upset-tolerant latch without the MCE and DICE modules. For the N-Node-Upset-Tolerant latch, the proposed RHBD latch only consists of N input-split inverters, 2N CMOS transmission gates and one Schmidt trigger. The generic design method is discussed, and a quadruple-node-upset-tolerant latch is designed and analyzed as an instance. The simulation results show that the RHBD latches designed by the proposed scheme consume less area and power compared with those previous counterparts.