Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel
Ang‐Sheng Chou, Ching-Hao Hsu, Yu‐Tung Lin, Goutham Arutchelvan, Edward Chen, Terry Y.T. Hung, Chen-Feng Hsu, Sui-An Chou, Tsung-En Lee, Oreste Madia, G. Doornbos, Yuan-Chun Su, Amin Azizi, D. Mahaveer Sathaiya, Jin Cai, Jer-Fu Wang, Yun-Yan Chung, Wen-Chia Wu, Katie Neilson, Wei‐Sheng Yun, Yu-Wei Hsu, Ming-Chun Hsu, Fa-Rong Hou, Yun-Yang Shen, Chao-Hsin Chien, Chung-Cheng Wu, Jeff Wu, H.‐S. Philip Wong, Wen‐Hao Chang, Mark van Dal, Chao-Ching Cheng, Chih‐I Wu, Iuliana Radu
Abstract
Two-dimensional (2D) transition metal dichalcogenide (TMD) materials are regarded as promising channel candidates for extreme contacted gate pitch (CGP) scaling. However, basic demonstration of the modules required to build logic devices is limited. For the first time, we demonstrate comparable n-type and p-type high-performance on 2D transistors. Translation to 300 mm wafer processing is tested by die-by-die transfer of the 2D material. The 300 mm fabrication preserves a relatively high mobility of 30 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V•s. We demonstrate scaling of nMOS contact length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> ) to 12 nm and top gate length (L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> ) to 10 nm. Devices maintain high current density at short L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</inf> as well as in top-gate only operation.