Reduction of Corner Effect in ZG-ES-TFET for Improved Electrical Performance and its Reliability Analysis in the Presence of Traps
Tammisetti Ashok, Chandan Kumar Pandey
Abstract
In this paper, various electrical parameters of a Z-shaped gate elevated source TFET (ZG-ES-TFET) in the presence of interface traps are investigated. The placement of Z-shaped gate across the elevated source region enhances the line tunneling in both horizontal and vertical direction, which eventually increases the device ON-current. Moreover, the L-shaped pocket placed above the elevated source region increases the rate of carriers tunneling into the channel region and improves the drain current in ZG-ES-TFET. In addition to this, the optimization of channel portion below the source region limits the corner effects, suppress the OFF-state leakage and which in turn leads to achieve high switching ratio in the proposed ZG-ES-TFET. Simulation results revels that ZG-ES-TFET shown improvement in switching ratio (I ON /I OFF ) and ON-current (I ON ) by an order of ∼2 and ∼1 as when compared to conventional LTFET. Thereafter, improvement in the carrier’s tunneling rate at source-channel (S-C) interface shows a significant enhancement in the transconductance (∼76.4 μ s μ m −1 ) of ZG-ES-TFET. It further helps to achieve a high cut-off frequency and Gain-Bandwidth-Product (GBW) of ∼6.9 GHz and ∼1.3 GHz, respectively. In reliability concern, the transfer characteristics of the proposed ZG-ES-TFET found to be less sensitive towards the presence of interface traps and temperature variations.