Low‐Temperature Polysilicon Oxide Thin‐Film Transistors with Coplanar Structure Using Six Photomask Steps Demonstrating High Inverter Gain of 264 V V<sup>−1</sup>
Duk Young Jeong, Yeoungjin Chang, Won Gyeong Yoon, Youngbin Do, Jin Jang
Abstract
The low‐temperature polysilicon oxide (LTPO) complementary metal‐oxide‐semiconductor (CMOS) thin‐film transistors (TFTs) is fabricated by p‐type low‐temperature polysilicon (LTPS) TFT and n‐type amorphous indium‐gallium‐zinc oxide (a‐IGZO) TFT using coplanar structure. A double‐stack SiO 2 layer deposited by high temperature first and then low‐temperature process is used as a gate insulator for LTPS TFT, leading to reduce the number of photomask steps. The p‐channel LTPS TFT of the fabricated LTPO circuits exhibits the field‐effect mobility ( μ FE ) and threshold voltage ( V TH ) of 89.9 cm 2 (V s) −1 and −5.5 V, respectively. However, the a‐IGZO TFT exhibits the μ FE of 22.5 cm 2 (V s) −1 and V TH of −1.3 V. Both the LTPS TFT and a‐IGZO TFT show excellent bias stability (Δ V TH of <0.1 V) and zero hysteresis voltage, which reveals the excellent interface between gate insulator and semiconductor. The LTPO CMOS inverter exhibits a gain of 264.5 V V −1 and a high noise margin of 4.29 V, and a low noise margin of 3.69 V at V DD of 8 V. Therefore, the LTPO TFT technology developed in this work can be a promising candidate for low cost, large‐area manufacturing of display, and TFT electronics.