SiO<sub>2</sub> Fin-Based Flash Synaptic Cells in AND Array Architecture for Binary Neural Networks
Soochang Lee, Hyeongsu Kim, Sung‐Tae Lee, Byung‐Gook Park, Jong‐Ho Lee
Abstract
An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) with sub-pA off current, and a low programming voltage (< 9 V) is used to achieve a sufficient dynamic range of synaptic weights (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only < 0.5 % degradation of classification accuracy compared to the baseline accuracy, which is suitable to perform off-chip event-driven computation using parallel read-out operations.