MSC-PoL: An Ultra-Thin 220-A/48-to-1-V Hybrid GaN-Si CPU VRM with Multistack Switched Capacitor Architecture and Coupled Magnetics
Ping Wang, David M. Giuliano, Stephen Allen, Minjie Chen
Abstract
This paper presents an ultra-thin microprocessor voltage regulator module (VRM) based on multistack switched-capacitor point-of-load (MSC-PoL) architecture and coupled magnetics. In the MSC-PoL architecture, the stacked switched-capacitor cells split the high input voltage into multiple intermediate voltage rails, which are loaded with the switched-inductor cells to achieve soft-charging and voltage regulation. Many inductors of the switched-inductor cells are coupled into one and operated in interleaving to miniaturize the dc magnetic energy storage, reduce the inductor current ripple, and improve the VRM transient speed. A 48 V-to-1 V, 6-mm-thick MSC-PoL VRM with ladder-structured coupled inductors is built and tested. A leakage magnetic plate of 0.8-mm thickness is designed to adjust the leakage inductance for lower current ripple. The peak efficiency, full-load efficiency and full-load power density of the MSC-PoL prototype with and without using the leakage plate are 92.9% and 91.2%, 86.3% (@220 A) and 85.1% (@210 A), and 607 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> and 677 W/in <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> , respectively.