Gate Driver Development and Stray Inductance Extraction of 10 kV SiC MOSFET Module for a Switched-Capacitor MMC Application
Zhehui Guo, Hui Li, Fang Zheng Peng, Michael Steurer, K.J. Olejniczak
Abstract
This paper presents gate driver (GD) development and stray inductance extraction for a 10 kV SiC MOSFET XHV-9 half-bridge module applied in a medium-voltage (MV) switched-capacitor modular multilevel converter (SC-MMC). The adopted GD architecture eliminates the common-mode (CM) noise on the signal path as well as enhances the CM transient immunity (CMTI) and reduces the CM capacitance of the GD power supplies (GDPSs). The GD PCB layout design achieves a minimized gate loop, active miller clamping loop and desat detection loop as well while preserving sufficient insulation distances for a 6 kV operating voltage. An ultra-fast desat protection circuit with optimized parameters is developed to effectively protect the 10 kV SiC MOSFETs. A fault-latching auto-reset circuit is proposed without adding extra fiber-optic (FO) communications. As part of the dc-loop of the SC-MMC, the stray inductance of a 10 kV SiC MOSFET XHV-9 half-bridge module is extracted by a two-port S-parameter measurement approach. The test fixture parasitics are identified and compensated to improve the accuracy. The developed GD performance is validated by the experiments at a 4.8 kV rated voltage, including the double-pulse test, multiple-pulse test and short-circuit protection test.