Thermoelectric Property Requirements for On-Chip Cooling of Device Transients
Lakshmi Amulya Nimmagadda, Sanjiv Sinha
Abstract
Power dissipation in semiconductor devices peak over short durations with scales much shorter than the thermal time constant. The typical heat sink is too far away from the junction hotspot to provide effective temporal cooling over such durations. Here, we theoretically explore on-chip Peltier cooling over short (~100 ms) durations, as a potential solution for managing transients near the junction. Choosing a simple unipolar Peltier device, we evaluate the thermoelectric property requirements for achieving net cooling using a steady Peltier current. Net cooling occurs when the peak transient temperature rise is reduced in the presence of an operating thermoelectric device in comparison with that in its absence. When the substrate is bulk silicon, a large power factor (>50 mW/mK <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and thermal conductivity (>100 W/mK) are required for net cooling. The requirement is less stringent and the impact more promising in wide-bandgap electronics with low conductivity substrates, where Peltier cooling reduces the impact of interface thermal resistance. This study points out materials research priorities for on-chip Peltier cooling and paves the way for effective realization of transient thermal management in proximity to the junction.