DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study
Martin Rack, Lucas Nyssens, Sidina Wane, Damienne Bajon, Jean‐Pierre Raskin
Abstract
In this paper, ultra-wideband SPDTs fabricated in the 22 nm FD-SOI process from GLOBALFOUNDRIES are presented. Three SPDT modules were implemented, each using a different type of millimeter-wave NFET, namely a conventional-well regular-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> (RVT) device, a flipped-well super-low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> (SLVT) device and a specially treated device without back-gate well contact for decreased substrate parasitics (BFMOAT device). It is shown that using the back-gate achieves lower losses, higher isolation and better linearity for the RVT and SLVT based switches, while the reduced parasitic BFMOAT switch shows better performance at the high-end of the mm-wave spectrum.