Wafer-scale fabrication of carbon-nanotube-based CMOS transistors and circuits with high thermal stability
Nan Wei, Ningfei Gao, Haitao Xu, Zhen Liu, Lei Gao, Haoxin Jiang, Yu Tian, Yufeng Chen, Xiaodong Du, Lian‐Mao Peng
Abstract
Thanks to its single-atomic-layer structure, high carrier transport, and low power dissipation, carbon nanotube electronics is a leading candidate towards beyond-silicon technologies. Its low temperature fabrication processes enable three-dimensional (3D) integration with logic and memory (static random access memory (SRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.) to realize efficient near-memory computing. Importantly, carbon nanotube transistors require good thermal stability up to 400 °C processing temperature to be compatible with back-end-of-line (BEOL) process, which has not been previously addressed. In this work, we developed a robust wafer-scale process to build complementary carbon nanotube transistors with high thermal stability and good uniformity, where AIN was employed as electrostatic doping layer. The gate stack and passivation layer were optimized to realize high-quality interfaces. Specifically, we demonstrate 1-bit carbon nanotube full adders working under 250 °C with rail-to-rail outputs.