Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
Eunbin Park, Taigon Song
Abstract
Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.