Scaling of double-gated WS<sub>2</sub> FETs to sub-5nm physical gate length fabricated in a 300mm FAB
Quentin Smets, T. Schram, Devin Verreck, Daire Cott, Benjamin Groven, Zubair Ahmed, B. Kaczer, Jérôme Mitard, Xiangyu Wu, Souvik Kundu, Hans Mertens, D. Radisic, Arame Thiam, Waikin Li, Emmanuel Dupuy, Zheng Tao, K. Vandersmissen, T. Maurice, Dennis Lin, P. Morin, Inge Asselberghs, Iuliana Radu
Abstract
We present an analysis of gate length scaling of WS2 transistors fully fabricated in a 300mm pilot line. Despite low channel mobility, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\max}=100\mu \mathrm{A}/\mu \mathrm{m}$</tex> is enabled by low side contact resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\mathrm{c}}=1.3\pm 1.0\mathrm{k}\Omega-\mu \mathrm{m}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$n=3\times 10^{13}\text{cm}^{-2}$</tex> . Hysteresis of 5m V/V at moderate electric fields is demonstrated. High single-device yield and low variability is achieved, and it is established that <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\text{on}}$</tex> correlates mainly with mobility and less with SS and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\mathrm{t}}$</tex> . We demonstrate that switch-off can still be achieved with extremely scaled <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\mathrm{g}}=2\text{nm}$</tex> , but significant short-gate effects occur due to thick CET and unoptimized device configuration. We show better short-gate control with connected dual gate configuration. TCAD simulations identify the main performance bottlenecks and a path towards improved device performance over Silicon FETs.