Multichannel Two-Dimensional MoS₂ Nanosheet MOSFET for Future Technology Node
Akhilesh Rawat, Brajesh Rawat
Abstract
In this work, we explore the 3-D integration of single layer (SL) and bilayer (BL) MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> in stacked gate-all-around (GAA) nanosheet field-effect transistor (NS-FET) using fully calibrated TCAD simulation for the future technology node. Our research primarily focuses on a comparative analysis between multichannel stacked SL-and BL-MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> NS-FETs with various-width Si NS-FETs, which show that BL-MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> NS-FET outperforms its Si NS-FET counterpart for sub-5-nm technology nodes. The results show that the vertical stacking of SL-and BL-MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> NS-FET significantly enhances the switching performance metrics and provides strong immunity against short-channel effects at aggressively scaled technology nodes over 50-nm wide Si NS-FET counterpart. On the other hand, the Schottky barrier (SB)-type contact with MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> NS-FETs is found to have inferior ON-state and OFF-state characteristics compared to doped-type contacts. Moreover, the CMOS inverter based on BL-MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> demonstrates the potential for lower power consumption at iso-frequency and higher operating frequency at iso-power compared to SL-MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> and Si NS-FETs. Our research underscores that MoS <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textsubscript{\text{2}}$</tex-math> </inline-formula> with stacked NS-FETs offers a promising solution for advancing technology nodes to 1 nm and beyond.