Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections
A. Vandooren, Narendra Parihar, J. Franco, Roger Loo, H. Arimura, R. Rodrı́guez, Farid Sebaai, Serena Iacovo, K. Vandersmissen, W. Li, G. Mannaert, D. Radisic, Erik Rosseel, Andriy Hikavyy, A. Jourdain, O. Mourey, G. Gaudin, S. Reboh, Lucie Le Van‐Jodin, G. Besnard, C. Roda Neve, B.-Y. Nguyen, Ionut Radu, E. Dentoni Litta, Naoto Horiguchi
Abstract
3D sequential stacking is demonstrated using top tier FDSOI devices on bottom tier bulk finFETs. 3D integration and top-bottom layer interconnectivity is validated through functional 3D via chains, 3D CMOS single inverters and inverter chain with transistors built in the top and bottom layers. Three different Si layer transfer flows, including a low temperature Smart Cut™, are investigated and compared electrically for top tier planar devices. Transfer of bi-axial tensile strained silicon is demonstrated with a 60-80% performance boost of the top tier nMOS device over the unstrained silicon devices. Further process optimization of the low temperature Smart Cut™ transfer provided significant electron and hole mobility recovery of the top tier devices. Impact of the stacking on bottom tier finFET devices is also studied for various bottom gate stacks.