Gate - Stack Dual Metal (DM) Nanowire FET with Enhanced Analog Performance for High Frequency Applications
Neeraj Neeraj, Shobha Sharma, Anubha Goel, Sonam Rewari, R.S. Gupta
Abstract
A Gate-Stack dual metal nanowire field effect transistor (4H- Silicon Carbide) is analyzed using ATLAS 3-D device simulator to enhance the analog performance of semiconductor devices for high frequency applications. Gate- Stack dual metal nanowire field effect transistor (4H-SiC) results have been compared with Nanowire field effect transistor, Nanowire field effect transistor having (Silicon Carbide Substrate) and dual metal nanowire field effect transistor (Silicon Carbide) substrate. This is done by introducing a Gate-Stack having high k-dielectric material, Hafnium oxide (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) along with Aluminum oxide (Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) gate dielectric. It exhibits higher drain current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> , Transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m)</sub> , output conductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d)</sub> and cut off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T)</sub> . The subthreshold slope obtained for gate -stack dual metal nanowire field effect transistor (4H-SiC) is 63.96 (mV/decade) which is closest to the ideal value as compared to other analogous nanowire field effect transistor which makes it extremely superior for high frequency applications.