6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET
Jay Im, Kevin Zheng, Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yipeng Wang, Hao-Wei Hung, KeeHian Tan, Winson Lin, Arianne Roldan, Declan Carey, Ilias Chlis, Ronan Casey, Ade Bekele, Ying Cao, David Mahashin, Hong Jo Ahn, Hongtao Zhang, Yohan Frans, Ken Chang
Abstract
Interest in 112Gb/s wireline transceivers targeting data center and communication applications has rapidly increased. PAM-4 signaling remains the dominant choice of modulation scheme due to its superior spectral efficiency [1-2]. This paper reports a long-reach-capable 112Gb/s PAM-4 transceiver designed in 7nm FinFET. Figure 6.1.1 illustrates the top-level block diagram of the transceiver, comprised of a shared LC-PLL, a transceiver channel, and a control block. The control block sends 875MHz 128b-wide TX data and receives 778MHz 144b-wide RX data to and from transceiver channels and calculates the PRBS bit error rate (BER). The LC-PLL synthesizes a 14GHz differential clock from a 583.33MHz external reference clock. The PLL output clock is then delivered to each channel via supply-regulated CMOS high-speed clock distribution buffers. TX architecture shown in Fig. 6.1.1 adopts a 4-tap FFE and a quarter-rate clocking scheme with duty cycle and I/Q mismatch calibration to enable the use of a power-efficient CMOS 4:1 MUX [4]. The I/Q error is sensed by replica MUXs and background calibrated with a 100fs resolution. Pad driver topology [4-5] is chosen to achieve 3% FIR resolution without an excessive power penalty from the large number of unit cells as would be required in a voltage-mode driver. A distributed inductor peaking network is designed to compensate for >200fF device and parasitic capacitance at the current summing node. A series inductor and a T-coil provide isolation between ESD diodes, C4 bump pad and on-die termination (ODT) resistors to effectively form a broadband lumped transmission line.