First Demonstration of W-Doped In<sub>2</sub>O<sub>3</sub> Gate-All-Around (GAA) Nanosheet FET with Improved Performance and Record Threshold Voltage Stability
Eknath Sarkar, Chengyang Zhang, Dyutimoy Chakraborty, Faaiq G Waqar, Sharadindu Gopal Kirtania, Khandker Akif Aabrar, Hyeonwoo Park, Jaewon Shin, Mengkun Tian, Asif Islam Khan, Shimeng Yu, Suman Datta
Abstract
We demonstrate a gate-all-around (GAA) nanosheet FET using an atomic layer deposited (ALD) tungsten (W) doped indium oxide (In<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>) or IWO channel. We developed a novel channel release process with a metal sacrificial layer (SL), that enables lithography-independent definition of the device channel length (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ch</inf>). The fabricated nanosheet FETs with scaled dimensions of L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ch</inf>=50nm and W<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Nanosheet</inf>=30nm demonstrate high on-state current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>) of 815 μA/μm for V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf>=1V, V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>-V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>=3.5V with an off-state current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf>) of 4 nA/um at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>=V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>-1V. These GAA nanosheet IWO FETs showcase record high bias stress stability with threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>) shift of only 88mV for stress voltage V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> - V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>=2.6V (stress field, E<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf>=V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ov</inf>/EOT=22 MV/cm). The high I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> of GAA nanosheet FET, along with its BEOL compatibility, enables access transistors for 3D stacked embedded MRAM, with peripheral CMOS under the array, consequently improving the cell density by 3.4x compared to conventional MRAM with front-end-of-line (FEOL) access transistors.