An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
Marcel Runge, Julius Edler, Tobias Kaiser, Kai Misselwitz, Friedel Gerfers
Abstract
This article presents a highly linear continuous-time (CT) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator incorporating energy-efficient open-loop GmC integrators with 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm {V_{ppd}}$ </tex-math></inline-formula> full-scale (FS) voltage. The second-order loop filter is inherently linearized using an input voltage tracking technique. Here, the modulator input and digital to analog converter (DAC) feedback signal have the same linear and non-linear voltage to current conversion. Subtracted in the current domain in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{A{m}}$ </tex-math></inline-formula> -stage, the non-linear contributors are eliminated and a highly linear wide-swing open-loop filter architecture is obtained. Linearity impairments due to tracking errors between the feedback DAC signal and the modulator input are analytically discussed and optimizations are introduced. The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> architecture takes advantage of a single feedback DAC which is shared among both the GmC integrators within the loop filter. A first-order finite impulse response (FIR) filter incorporated in the single feedback DAC is implemented by two 5-bit time-interleaved source-series terminated (SST) DACs comprising a data-dependent supply impedance compensation. Fabricated in a 22-nm FD SOI process, the 18-MS/s prototype consumes 3.21 mW combined from a 0.9- and 1.3-V power supply. Revealing 93-dB spurious free dynamic range (SFDR) at 76.5-dB peak signal to noise and distortion ratio (SNDR) performance, the prototype design achieves a 171-dB figure of merit (FoM) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</sub> with only 41-fF input capacitance.