Trap Capture and Emission Dynamics in Ferroelectric Field-Effect Transistors and their Impact on Device Operation and Reliability
Nujhat Tasneem, Zheng Wang, Zijian Zhao, Navnidhi K. Upadhyay, Sarah Lombardo, Hang Chen, Jae Hur, Dina H. Triyoso, Steven Consiglio, Kandabara Tapily, Robert D. Clark, Gert J. Leusink, Santosh Kurinec, Suman Datta, Shimeng Yu, Kai Ni, M. Passlack, Winston Chern, Asif Islam Khan
Abstract
We track carrier capture and emission dynamics during write operations in n-type ferroelectric-field-effect transistors (FEFETs) by directly and separately measuring the trap related hole and electron currents through the body terminal and shorted source-drain, respectively. Both electron and hole currents are simultaneously observed during polarization switching, irrespective of whether the channel is in hole accumulation or electron inversion. This allows us to discover the exact mechanism of emission and capture of carriers, which leads to partial neutralization of the traps charged in the previous write cycle. With fatigue cycling, the neutralization of trapped charges progressively decreases, and the density of trap states increases leading to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{G}$</tex> , SS and peak <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$g_{m}$</tex> degradation. An increase in the effective time constant of trap states is also evident with cycling as a fatigued FEFET requires longer time to reach a given memory window after a write operation. We conclude that the memory window in FEFETs is facilitated by neutralization of traps, previously charged by carriers captured during FE switching (i. e., write operation) that screen the ferroelectric polarization. These emission and capture dynamics place the trap levels close to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{c}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$E_{v}$</tex> and inside the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and at the SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /HZO interface, and currently hinders high-speed read-after-write in front-end FEFETs. The universality of the suggested mechanisms is confirmed in FEFETs fabricated in different facilities.