Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell
Ayush Kanojia, Sachin Agrawal, Rohit Lorenzo
Topics & Concepts
AdderComputer scienceSerial binary adderPower–delay productCarry-save adderStandard cellChipScheme (mathematics)Computer hardwarePower (physics)16-bitTransistorElectronic engineeringVoltageElectrical engineeringIntegrated circuitTelecommunicationsMathematicsLatency (audio)EngineeringQuantum mechanicsMathematical analysisPhysicsOperating systemLow-power high-performance VLSI designVLSI and FPGA Design TechniquesAdvancements in Semiconductor Devices and Circuit Design