Trap Analysis Based on Low-Frequency Noise for SiC Power MOSFETs Under Repetitive Short-Circuit Stress
J. L. Wang, Yiqiang Chen, Jingtai Feng, Xinbing Xu, Yunfei En, Bo Hou, Rui Gao, Yuan Chen, Yongzhang Huang, K. W. Geng
Abstract
In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on low-frequency noise (LFN) was carried out for the commercial 1.2-kV/30-A silicon carbide (SiC) power MOSFETs under repetitive short-circuit (SC) stress. The experiment results show that the on-state resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dson</sub> ) and threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) increase significantly. Meanwhile, the drain-source current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> ) decreases obviously with the increase of the SC cycles. Furthermore, the gatesource leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gss</sub> ) of the SiC power MOSFETs increase greatly and the blocking characteristics deteriorated after 1000 SC cycles. The positive shift was observed on the gate-capacitance versus gatevoltage (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) curve, which shows that the damage region could be in channel along the SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface after repetitive SC stress. In order to obtain the trap information, trap characterization was performed by using LFN method, and the LFN results show that the trap density increases with the SC cycles. The physical mechanism could be attributed to electrically active traps generated at SiC/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface and oxide layer due to the peak ionization rate, the perpendicular electrical field and high temperature during SC stress. The study may be useful to provide reference for converters design and fault protection of SiC power MOSFETs.