Development of a processing map for safe flash sintering of gadolinium‐doped ceria

Abstract

Abstract Flash sintering was discovered in 2010, where a dog‐bone‐shaped zirconia sample was sintered at a furnace temperature of 850°C in <5 s by applying electric fields of ~100 V cm −1 directly to the specimen. Since its discovery, it has been successfully applied to several if not all oxides and even ceramics of complex compositions. Among several processing parameters in flash sintering, the electrical parameters, i.e., electric field and electric current, were found to influence the onset temperature for flash and the degree of densification respectively. In this work, we have systematically investigated the influence of the electrical parameters on the onset temperature, densification behavior, and microstructure of the flash sintered samples. In particular, we focus on the development of a processing map that delineates the safe and fail regions for flash sintering over a wide range of applied current densities and electric fields. As a proof of concept, gadolinium‐doped ceria (GDC) is shown as an example for developing of such a processing map for flash sintering, which can also be transferred to different materials systems. Localization of current coupled with hot spot formation and crack formation is identified as two distinct failure modes in flash sintering. The grain size distribution across the current localized and nominal regions of the specimen was analyzed. The specimens show exaggerated grain growth near the positive electrode (anode). The region adjacent to the negative electrodes (cathode) showed retarded densification with large concentration of isolated pores. The electrical conductivity of the flash sintered and conventional sintered samples shows identical electrical conductivity. This quantitative analysis indicates that similar sintering quality of the GDC can be achieved by flash sintering at temperature as low as 680°C.

Topics & Concepts