A 0.39-mm² Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC

Abstract

This article reports an energy/area-efficient zoom capacitance-to-digital converter (CDC)-based CMOS humidity sensor. It achieves the best-in-class error of ±0.8%RH and better figure of merit (FoMw; 87 fJ/c.step) than the state-of-the-art humidity sensors due to the use of the two techniques described in the following: 1) a charge-redistribution correlated level-shifting (CR-CLS) floating inverter amplifier (FIA) is proposed to increase the conventional CLS-FIA open-loop gain by at least 13.5 dB across temperature variations (−40 °C to 85 °C) and the extreme process corners, minimizing the closed-loop FIA gain error and thus the CDC nonlinearity and humidity error and 2) a pair of stacked humidity sensors over the circuits, all of which are included in the standard CMOS process, is proposed to achieve a lower cost and decrease the area by half. The proposed CMOS humidity sensor is implemented in a 55-nm CMOS process. The measurement results show that the capacitance resolution and humidity resolution are 197 aF and 0.094%RH, respectively, at a total input capacitance of 3 pF, and the effective number of bits (ENOB) is 12.1 at a clock frequency of 2.5 MHz and a cycle number per conversion (N) of 16. The proposed humidity sensor consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$9.57 \mu \text{W}$ </tex-math></inline-formula> at the conversion time of 0.04 ms. The sensor exhibits a ±0.8%RH peak-to-peak accuracy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula> error of 2.5%RH) among 40 chips from 20%RH to 85%RH.

Topics & Concepts