Benchmarking of Multi-Bridge-Channel FETs Toward Analog and Mixed-Mode Circuit Applications
V. Bharath Sreenivasulu, N. Aruna Kumari, Asisa Kumar Panigrahy, Lokesh Vakkalakula, Jawar Singh, Shiv Govind Singh
Abstract
In this study, for the very first time developing of n- and p-type 3-D single-channel (SC) FinFET and Multi-Bridge-Channel (MBC) gate-all-around (GAA) FETs are benchmarked on both the device and circuit levels and compared to the IRDS for sub-5-nm technology nodes. The performance of FinFET, nanowire (NW) and nanosheet (NS) FETs are compared at the same effective width ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ) and threshold voltages ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ). Compared to the SC FinFET the MBC GAA NWFET and NSFET exhibits higher ON-current ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), switching ratio ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> / <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ), lower subthreshold-swing (SS) and drain-induced barrier lowering (DIBL) at equal <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> . Except for extended parasitic capacitances ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</sub> ), our benchmarking results show that the NWFET and NSFET achieves the high-performance (HP) and low-power (LP) goals of (International Road map for Devices and Systems) IRDS. Furthermore, the NSFET delivers the superior performance towards DC and analog/RF metrics. The cut-off frequency ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and GBW are higher (because of high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) in the case of NSFET, even though the capacitive effect is significant. Further, the logic circuit applications like CMOS inverter and ring oscillator (RO) are analyzed and compared in detail. The CMOS inverters propagation delays (τ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</sub> ) is reduced to 31% from FinFET to NWFET and 12% from NWFET to NSFETs is noticed. Also, the NWFET and NSFET based ROs offer 39% and 56% high oscillation frequency ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">osc</sub> ) compared to that of FinFET counterpart. Finally, the single stage current mirror performance and operational transconductance amplifiers (OTA) gain and common mode rejection ratio (CMRR) is carried out towards analog and mixedmode circuit applications.