17.8 A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS
Qian Chen, Yuan Liang, Chirn Chye Boon, Qing Liu
Abstract
High data throughput and wideband network communications demand high-speed (several to tens of GS/s), moderate-resolution (6–10b) ADCs. The emerging time-domain ADC (TD-ADC) has been gaining more interest because of its energy efficiency and area efficiency [1], [2], providing a promising solution for high-speed architectures. However, the speed superiority of the TD-ADC, enabled by time-domain quantization, has not been sufficiently leveraged due to the long waiting time allocated for multiple bit decisions, which consumes the conversion period [1]–[3]. In addition, the voltage-to-time converter (VTC) front end suffers from linearity degradation at high frequencies (10GHz) [4]. In this work, we have implemented an asynchronous successive approximation (ASA) time-to-digital converter (TDC), significantly improving the throughputs through time-domain pipeline operation. Furthermore, reliability is guaranteed without adding extra delay in the clock path due to the inherent robust synchronization scheme of ASA. On the other hand, the VTC nonlinearity is compensated by optimizing the reference delays in the ASA TDC, utilizing the least-mean-square (LMS) tuning at the circuit design stage. To demonstrate the speed superiority of the TD-ADC, a prototype single-channel ADC was fabricated in 28nm CMOS, achieving 36.4dB SNDR, 58.9fJ/conv.-step figure-of-merit (FoM) at 10GS/s with Nyquist input, occupying 0.009mm2 active area, and presenting the fastest single-channel speed compared to other state-of-the-art of ADCs with 8b resolution.