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A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC

Yunshan Zhang, Changgui Yang, Junhong Sun, Zhuhao Li, Huan Gao, Yuxuan Luo, Kedi Xu, Gang Pan, Bo Zhao

2022IEEE Transactions on Biomedical Circuits and Systems21 citationsDOI

Abstract

Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 10 effective number of bits (ENOB) and sub- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula> W in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu V_{rms}$</tex-math></inline-formula> in a bandwidth of 0.9 Hz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$-$</tex-math></inline-formula> 7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-vivo</i> demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-vivo</i> neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.

Topics & Concepts

ChipCMOSComputer scienceAlgorithmElectrical engineeringArtificial intelligenceEngineeringAnalog and Mixed-Signal Circuit DesignAdvanced Memory and Neural ComputingNeuroscience and Neural Engineering
A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC | Litcius