Radiation Hardness Study of <i>L</i> <sub>G</sub> = 20 nm FinFET and Nanowire SRAM Through TCAD Simulation
Adam Elwailly, Johan Saltin, Matthew J. Gadlage, Hiu Yung Wong
Abstract
Radiation hardness of FinFET and stacked nanowire (NW) static random-access memory (SRAM), with L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 20 nm, which corresponds to high-density 5 nm technology node, is studied and compared using 3-D technology computer-aided design (TCAD) full cell domain simulation. Single FinFET and NW of similar total height are created using process simulation. Two types of NWs are studied, namely, high-performance and low-power NW, which has the same OFF-state and ON-state current as the FinFET, respectively. Device simulations are performed using transport parameters calibrated in Monte Carlo simulations. Radiation hardness of both n-type and p-type devices are simulated by striking particles at various locations and directions when the transistors are at OFF-state. It is found that NW is more robust than FinFET in all strike locations and directions. Radiation strikes are then applied to the OFF-state transistors in the SRAM at the most vulnerable positions. The SRAMs of both devices are designed to have similar noise margins for a fair comparison. It is found that NW SRAM is much more robust and can sustain two to three times higher linear energy transfer (LET) than FinFET SRAM in the most striking locations. Therefore, from a radiation robustness perspective, NW SRAM is preferred.