An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier
Myungjun Kim, SeongHwan Cho
Abstract
In this paper, we propose an output-capacitorless analog low-dropout voltage regulator (ALDO) featuring frequency compensation of a four-stage amplifier consisting of a three-stage error amplifier (EA) without cascoding plus a last stage formed by a pass transistor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {M_{P}}$ </tex-math></inline-formula> ). It achieves good output voltage regulation under low supply-voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula> ) with an unsaturated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {M_{P}}$ </tex-math></inline-formula> (e.g., dropout voltage of 30 mV under 0.5 V supply) because of the three gain stages in the EA. Frequency compensation is achieved by performing a two-port feedback analysis with the root-locus diagram (TFR) method that provides an intuitive understanding of pole/zero dynamics in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$s$ </tex-math></inline-formula> -plane. Fabricated in 0.18 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS, the proposed ALDO achieves asymptotic stability over a wide range of operating conditions: <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5\sim 1.8$ </tex-math></inline-formula> V, load capacitance of 0~50 pF, load current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{L}$ </tex-math></inline-formula> ) of 0~2 mA (0~200 mA) under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{dd}$ </tex-math></inline-formula> of 0.5 V (1.8 V), and temperature of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 20\sim 125\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . Also, it does not require minimum on-chip output capacitance, thus achieving a small area of 0.0035 mm2. As a result, a good low-frequency PSR of −62 dB with a dropout voltage of 30 mV and a state-of-the-art current density of 11.4 A/mm2 are achieved.