LSPWM, PSPWM and NLCPWM on multilevel inverters with reduced number of switches
V. Ramu, P. Satish Kumar, Gantasala Naga Srinivas
Abstract
Due to their generation of higher voltage levels, reduced harmonics, low power losses, reduced size and cost multilevel inverters (MLIs) are gaining acceptance. Increased number of voltage levels of MLIs will reduce total harmonic distortion compared to two level inverters. As dv/dt stress is low on each switch these inverters can be used in high voltage and high-power applications. Main drawback of MLIs is requirement of higher number of switch count. Due to increased number of switches, complexity in controlling strategy, overall cost and total size of the inverter increases. In this paper a topology of multilevel inverter is presented and various modulation strategies based on high and low switching frequencies are implemented. These modulation strategies are compared in terms of THD and efficiency of inverter for 17 level, 53 level and 71 level. All results show adequate performance of inverter with different modulation indices and loads. Compared with existing MLIs topologies this topology requires a smaller number of switches. Comparison with previous work is also presented in terms number of switches, number of DC sources, number of gate driver circuits and total blocking voltage.