A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB
Souvik Mahapatra, Aseer Ansari, Arnav Shaurya Bisht, Nilotpal Choudhury, Narendra Parihar, Payel Chatterjee, Prasad Gholve, Ravi Tiwari, Satyam Kumar, Tarun Samadder
Abstract
The Reaction-Diffusion-Drift model is validated as a trap generation framework during Bias Temperature Instability (BTI), Stress Induced Leakage Current (SILC), and Time Dependent Dielectric Breakdown (TDDB) experiments. The model is implemented in standalone and Technology CAD (TCAD)-based deterministic and standalone stochastic versions. Different implementations show equivalence of the time kinetics of trap generation during stress and trap passivation after stress. The trigger for different type of experiments is introduced via a single reaction parameter. The model is validated against measured data under diverse experimental conditions, either solely, or along with other models to account for additional physical processes. A circuit simulation platform that uses the physical trap generation model is utilized to estimate activity aware aging in logic circuits due to BTI. The error associated with effective AC duty simulation is shown. Implementation and validation for the Hot Carrier Degradation (HCD) is presented in part-II of this article.