Understanding and modelling the PBTI reliability of thin-film IGZO transistors
Adrian Chasin, J. Franco, K. Triantopoulos, H.F.W. Dekkers, Nouredine Rassoul, Attilio Belmonte, Quentin Smets, Subhali Subhechha, D. Claes, Michiel J. van Setten, Jérôme Mitard, Romain Delhougne, V. V. Afanas’ev, B. Kaczer, Gouri Sankar Kar
Abstract
We study the impact of the gate-dielectric on the Positive Bias Temperature Instability (PBTI) of IGZO thin-film transistors (TFT). We show that PBTI is controlled by the gate-dielectric pre-existent electron traps and its hydrogen content. The degradation process can be composed of up to four different mechanisms with different time kinetics, voltage acceleration factors and activation energies. A simplified physics-based model is used to reproduce stress and relaxation traces recorded in a wide range of test conditions. Gate-dielectric optimization enables scaled EOT (2.5nm) IGZO TFT to achieve a record lifetime of ~ 1 year continuous operation at 95°C and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{V}_{\text{ov}}=1\mathrm{V}$</tex> , with a strict failure criterion of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\vert \Delta \mathrm{V}_{\text{th}}\vert < 30\text{mV}$</tex> .