A Fully Integrated Mixed-Signal Compute-In-Memory Accelerator for Solving Arbitrary Order Boolean Satisfiability Problems
Tinish Bhattacharya, Dongseok Kwon, George Higgins Hutchinson, Xiangyi Zhang, Ignacio Rozada, Dmitri B. Strukov
Abstract
This paper presents a mixed-signal In-Memory Computing (IMC) accelerator with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$256 \times 128$</tex> 10T bi-directional SRAM array in 55 nm CMOS process, for solving arbitrary-order KBoolean Satisfiability (K-SAT) problems. It achieves nearly an order of magnitude faster solution times compared to other single-variable update ASIC solvers on uniform random 3-SAT problems, while outperforming all other solvers by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10 \div 200 \times$</tex> on the studied higher-order K-SAT problems, relevant to cryptography applications.