Dielectric Interface Engineering for High-Performance Monolayer MoS₂ Transistors via TaO_xInterfacial Layer

Abstract

Field-effect transistors (FETs) based on 2-D materials have great potential for future ultimate-scaled electronics. However, nonideal semiconductor–dielectric interfaces due to interfacial traps and oxide traps have constrained the potential of 2-D semiconductors. Here, we report a new dielectric interface engineering approach for monolayer (1L) MoS2 transistors employing a relatively high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa $ </tex-math></inline-formula> TaOx interfacial layer ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\kappa \sim $ </tex-math></inline-formula> 7) whose defect bands are located outside of the operation window of the MoS2 Fermi level. Such band alignment can minimize active interface trap states in top-gate (TG) dielectric stacks. The TaOx interfacial layer can also act as an efficient doping layer, with the highest ON-current <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> reaching 861 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}} $ </tex-math></inline-formula> = 1.5 V and overdrive voltage <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {OV}} $ </tex-math></inline-formula> = 3 V. The lowest contact resistance is down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$230 \Omega \cdot \mu \text{m}$ </tex-math></inline-formula> . Dual-gate (DG) FETs can achieve subthreshold slope (SS) values down to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 70 mV/dec in short-channel devices ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {CH}} =55$ </tex-math></inline-formula> –75 nm). Our reported SS, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> are among the best-reported values for MoS2 devices. For low-power applications, our devices exhibit a record-high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> of 598 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}} =0.65$ </tex-math></inline-formula> V. The new dielectric engineering approach proposed in this study can pave the way for realizing high-performance logic devices based on 2-D materials.

Topics & Concepts