Extended State-Based OSG Configurations for SOGI PLL With an Enhanced Disturbance Rejection Capability
Abdullahi Bamigbade, Vinod Khadkikar
Abstract
Changes in the orthogonal signal generator (OSG) configuration of the standard second-order generalized integrator-based phase-locked loop (S-SOGI PLL) have shown to offer an improved low-voltage ride-through capability. However, the resulting PLLs: highpass SOGI (H-SOGI) and lowpass SOGI (L-SOGI) PLLs have no dc-offset estimation capability and lack robustness to disturbances. Therefore, this article focuses on maximizing the merits of H-SOGI and L-SOGI PLLs for grid and industrial applications by incorporating dc-offset estimation and enhancing their disturbance rejection capability. Accordingly, two varieties of SOGI PLLs, namely: extended state highpass SOGI (ES-H-SOGI) and extended state lowpass SOGI (ES-L-SOGI) PLLs are proposed. In the proposed PLLs, states of the OSGs are extended to achieve dc-offset estimation and rejection, while frequency-adaptive implementation of the moving average filter (MAF) is developed to achieve complete harmonic rejection at off-nominal frequencies of the input voltage. To alleviate the undesirable effect of the MAF in terms of the PLL's slow transient response, frequency-adaptive implementation of a phase-lead compensator is introduced. In this article, design guideline that achieves an optimal tradeoff between disturbance rejection and dynamic performance in the ES-H-SOGI and ES-L-SOGI PLLs is presented. Finally, experimental comparison between the proposed ES-H-SOGI and ES-L-SOGI PLLs and their ES-S-SOGI PLL counterpart is carried to show that the proposed PLLs outperform the ES-S-SOGI PLL in terms of dynamic performance while achieving enhanced disturbance rejection capability.