SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture
Amirreza Yousefzadeh, Gert-Jan van Schaik, Mohammad Tahghighi, Paul Detterer, Stefano Traferro, Martijn Hijdra, Jan Stuijt, Federico Corradi, Manolis Sifalakis, Mario Konijnenburg
Abstract
SENeCA is our first RISC-V-based digital neuromorphic processor to accelerate bio-inspired Spiking Neural Networks for extreme edge applications inside or near sensors where ultra-low power and adaptivity features are required. SENeCA is optimized to exploit unstructured spatio-temporal sparsity in computations and data transfer. It is a digital IP, contains interconnected Neuron Cluster Cores, with RISC-V-based instruction set, an optimized Neuromorphic Co-Processor, and event-based communication infrastructure. SENeCA improves state of the art by: Addressing the flexibility issue in neuromorphic processors by allowing a fully programmable neuron model and learning/adaptivity algorithms; Improving the area efficiency by employing a 3-level memory hierarchy which allows using novel embedded memory technologies; Efficient deployment of advanced learning mechanisms and optimization algorithms by accelerating neural operations in three data types: int4, int8 and BrainFloat16; Efficient event communication by using a new Network-on-Chip with multicasting, a compression mechanism, and source-based routing. The implemented digital IP can be tuned for different applications to have a flexible number of cores and Neural Processing Elements (NPEs) per core and optional use of off-chip memory. Next to the hardware, the SENeCA platform includes an SDK and a hardware-aware simulator for close-loop synthesis/mapping optimization <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> The SENeCA platform is freely accessible for the academic purposes. .