Challenges of Wafer‐Scale Integration of 2D Semiconductors for High‐Performance Transistor Circuits
T. Schram, Surajit Sutar, Iuliana Radu, Inge Asselberghs
Abstract
Abstract Large‐area 2D‐material‐based devices may find applications as sensor or photonics devices or can be incorporated in the back end of line (BEOL) to provide additional functionality. The introduction of highly scaled 2D‐based circuits for high‐performance logic applications in production is projected to be implemented after the Si‐sheet‐based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D‐based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided. Today, typical test vehicles for 2D devices are single‐sheet devices fully integrated in a lab environment, but transfer to a more scaled device in a fab environment has been demonstrated. This work reviews the status of the module development, including considerations for setting up fab‐compatible process routes for single‐sheet devices. While further development on key modules is still required, substantial progress is made for MX 2 channel growth, high‐ k dielectric deposition, and contact engineering. Finally, the process requirements for building ultra‐scaled stacked nanosheets are also reflected on.