Capacitor-Based Synaptic Devices for Hardware Spiking Neural Networks
Sungmin Hwang, Junsu Yu, Geun Ho Lee, Min Song, Jeesoo Chang, Kyung Kyu Min, Taejin Jang, Jong‐Ho Lee, Byung‐Gook Park, Hyungjin Kim
Abstract
In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear <inline-formula> <tex-math notation="LaTeX">${C} - {V}$ </tex-math></inline-formula> characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.