Energy-Efficient Monolithic 3-D SRAM Cell With BEOL MoS<sub>2</sub> FETs for SoC Scaling
Vita Pi‐Ho Hu, Chengwei Su, Yen-Wei Lee, Tun-Yi Ho, Chao-Ching Cheng, Tzu-Chiang Chen, Terry Y.T. Hung, Jin-Fu Li, Yuguang Chen, Lain‐Jong Li
Abstract
In this article, we propose an energy-efficient monolithic 3-D (M3D) three-tier SRAM cell with back-end-of-the-line (BEOL) back-gated (BG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs. The impacts of wire routing resistance and capacitance, gate topology of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs, and the layout optimization of multitier 6T SRAM cells have been comprehensively analyzed for SoC scaling through system-technology co-optimization. SRAM plays an integral role in the performance of SoCs, and the performance can be improved by SRAM on logic integration. Compared with one-tier BG SRAM cell design, the proposed monolithic three-tier BG SRAM cell releases the impact of metal line resistance and shows a 44.3% reduction in cell area, 28.4% improvement in read access time, 21.3% improvement in dynamic energy, and 43.6% improvement in energy-delay product. The energy- and area-efficient three-tier BG SRAM cell enables intelligent functionalities for the area- and energy-constrained edge computing devices.