25.3 An 8Gb GDDR6X DRAM Achieving 22Gb/s/pin with Single-Ended PAM4 Signaling
Timothy M. Hollis, Ronny Schneider, M. Brox, Thomas Hein, W. Spirkl, Martin Bach, Mani Balakrishnan, Stefan Dietrich, Fabien Funfrock, Milena Ivanov, Natalija Jovanović, Maksim Kuzmenka, Daniel Lauber, Juan Ocon-Garrido, David Ovard, K. Peter Pfefferl, Sven Piatkowski, Gabriele Piscopo, Manfred Plan, Jens Polney, Jan Pottgiesser, Stephan Rau, Filippo Vitale, Marc Walter, Marcos Alvarez-Gonzalez, Martin Broschwitz, Cristian Chetreanu, Andrea Sorrentino, Joerg Weller, Peter Mayer, Michael Richter, Casto Salobrena Garcia, Andreas Schneider, Shih Nern Wong
Abstract
Several factors drive the demand for DRAM bandwidth scaling: in addition to established applications in visualization, there has been a proliferation of data-intensive applications enabled by advancements in AI, ML and advanced driver-assistance systems (ADAS) [1]. While high-bandwidth memory (HBM) provides an alternative solution, its high cost makes it impractical for many applications. On the other hand, extending the GDDR roadmap beyond GDDR6 through per-pin bandwidth scaling presents significant obstacles: including the reduced link-timing budget and the slow DRAM transistors. This paper introduces an 8Gb DRAM with a single-ended PAM4 interface to redirect and extend the GDDR roadmap. The design supports 22Gb/s/pin, a 22% increase over the highest published GDDR6 DRAM bandwidth [2], in a conventional 1Ynm DRAM process.