A Four-Element 7.5–9-GHz Phased-Array Receiver With 1–8 Simultaneously Reconfigurable Beams in 65-nm CMOS
Nayu Li, Min Li, Shaogang Wang, Zijiang Zhang, Huiyan Gao, Yen‐Cheng Kuan, Chunyi Song, Xiaopeng Yu, Qun Jane Gu, Zhiwei Xu
Abstract
This article presents a four-element 7.5-9-GHz phased-array receiver with 1-8 concurrent beams in a 65-nm CMOS technology. Each output beam utilizes all the input elements to maximize the beamforming gain. To realize a low-power and compact design, the multielement multibeam phased-array architecture features the gm-based variable-gain phase shifter (VG-PS) and the current-sharing active combiner. The VG-PS with 6-bit phase resolution achieves <; 2° root mean square (rms) phase error and <; 0.3 dB rms gain error at the maximum gain setting. The receiver demonstrates a 20-dB power gain, a 3.6-dB noise figure (NF), and a -19-dBm input 1-dB gain compression point (IP1dB) at 7.5-9 GHz for each element. The chip occupies $5.42\times3.62$ mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area excluding pads and consumes 860 mW, equivalent to the record low 27 mW per element per beam. To our knowledge, the receiver achieves the maximum number of simultaneously reconfigurable beams with the lowest power consumption per element per beam in RF phase shifting and combining receiver chips.