MCell

Yih-Lang Li, Shih‐Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera

202013 citationsDOI

Abstract

Multi-row cell structure has become popular for modern designs, especially for the multi-bit flip-flop (MBFF) cells, but has not been under full investigation in previous cell library synthesis researches. In this work, we propose an entire placement and routing flow for synthesizing multi-row cell layouts. The proposed new A*-based multi-row transistor placement algorithm can optimize the intra-row and inter-row connections. We also present the first MAX-SAT based detailed router to optimize the cross-row connections that also conform to primitive design rules, but not only to obtain a legal routing result in previous SAT-based detailed router. Experimental results show that the quality of synthesized cells is similar to that of a state-of-the-art cell library in [6], and better aspect ratios of multi-row cells also offer more flexible capability in assembling block designs under some aspect ratio constraints as compared to single-row cell library.

Topics & Concepts

RouterComputer scienceRouting (electronic design automation)Standard cellBlock (permutation group theory)Network routingIntegrated circuit layoutParallel computingComputer architectureComputer networkMathematicsIntegrated circuitGeometryOperating systemVLSI and FPGA Design TechniquesVLSI and Analog Circuit TestingLow-power high-performance VLSI design