A Compact 3–30-GHz 68.5-ps CMOS True-Time Delay for Wideband Phased Array Systems
Minjae Jung, Byung‐Wook Min
Abstract
This article presents a compact 4-bit switched-line true-time delay (TTD) circuit over a wide frequency range extending from 3 to 30 GHz using novel delay elements. The delay elements, namely, the cascading coupled all-pass network (CAPN) and noncoupled all-pass network (NCAPN), were employed in the proposed TTD circuit to improve the delay-bandwidth product (DBW) while maintaining its compact size and low delay variation (DV). For comparison, a theoretical analysis for understanding the group delay feature of the APN with various coupling coefficients is presented along with low-pass network (LPN). To verify the proposed structure, the proposed delays are applied to construct the 4-bit switched-line TTD by utilizing two single-pole double-through (SPDT) and three double-pole double-through (DPDT) switches in a 28-nm CMOS process. The circuit has a compact size of 1.7 mm ×0.2 mm, with a maximum delay of 68.5 ps and a minimum delay of 4.6 ps. The measured average insertion loss is 13.5 dB, and the in/out return loss is better than 10 dB across 3-30 GHz. The measured rms delay and gain errors are less than 2 ps and 3.2 dB, respectively, over the operating frequency range. To the best of our knowledge, the proposed TTD achieves the largest figure of merit (FoM) among the integrated TTD circuits.