Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior
Gianluca Giustolisi, G. Palumbo
Abstract
In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.
Topics & Concepts
Settling timeSettlingSlew rateStage (stratigraphy)Computer scienceElectronic engineeringOperational transconductance amplifierAmplifierTransconductanceOperational amplifierCMOSControl engineeringEngineeringElectrical engineeringStep responseTransistorVoltageEnvironmental engineeringBiologyPaleontologyAnalog and Mixed-Signal Circuit DesignAdvancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design